Résumé
Specifies the logical layer for a set of signal lines that constitute a multiple segment bus architecture, and for the interfacing of modules connected to a bus segment. Intended to be used as a component within a profile to build systems with higher levels of compatibility.
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État actuel: AnnuléeDate de publication: 1994-12
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Edition: 1
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- ICS :
- 35.160 Systèmes à microprocesseurs
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